1. Field of the Invention
The present invention is concerned with a computer system having a memory access circuit between data access circuitry (eg. a processor or similar data consumer) and main memory.
2. Discussion of the Related Art
One of the main restrictions on existing computing architectures and electronic circuits is the speed of read/write accesses to or from memory. Typical modern chipsets have a plurality of circuits connected by a common communication bus which compete for control of that bus to access main memory. The problem is compounded by the long latency exhibited by some memories, which often result in a data request not being completed in the cycles allotted to a requesting device for control of the communications bus.
FIG. 1 shows a system which illustrates this classic problem. A data consumer 2 is issuing read requests to a memory 6 via a common bus resource 4 using a linearly increasing DMA (Direct Memory Access) where each address is one word above the last in memory. The data consumer DMA 2 issues a series of sequential read requests 8 to the memory 6. Each request 8 requires a response (read data) 10 before a new request 8 can be made.
Other data consumers and providers (labelled “other devices” in FIG. 1) compete for the bus resource 4. For the bus resource 4 to be used efficiently, the data consumer 2 should use all the time it locks the bus resource to transfer data. In addition, the data consumer 2 will be more efficient if each word of data requested is returned as quickly as possible to it by the memory. However, the memory 6 has a long latency, and so each read request 8 takes many cycles to complete, thus making the data consumer 2 and bus resource 4 inefficient. In addition, the bus resource 4 may be locked for periods of time by the other devices, so that the data consumer may be starved of data for unacceptable periods.
The data consumer 2 may not be able to perform its function, given the low bandwidth of data it receives as a result of the latency for each read in the DMA.
One possible solution to this problem is to place a cache memory (not shown) at the boundary shown as “X—X” in FIG. 1. As read requests 8 are made, the cache is prefilled and requests can be satisfied directly from the cache. This works well to reduce the latency of the DMA reads and increase peak bandwidth. However, whenever there is a cache miss there will be an interruption while the cache is refilled. Another disadvantage with a cache solution is that it requires a custom silicon memory design.
An alternative known solution would be to use a FIFO (First In First Out) buffer at the boundary shown as “X—X”. Again, this allows requests to be satisfied directly from the FIFO, once it is full. However, refilling of the FIFO whenever it is empty introduces an interruption in the data provided.